THE HYPIX PROJECT:

Introduction:

 

 

The Hypix (Hybrid Pixels) project was a £3.8M EPSRC funded academic project formed by the collaboration of The University of Edinburgh, The University of Strathclyde, The University of St Andrews and Imperial College London. The project ran from Oct 2008 to Sept 2012, and aimed to produce hybrid pixels with a 2.5-D stacking structure. While the main project website is no longer active, some details of the project are held at: 

 

The stack was to be a hybrid GaN III-V LED structure (Strathclyde Photonics), that optically pumps an organic lasing polymer (Strathclyde Chemistry). The coupling of optical power into the organic polymer was to be through distributed feedback structures monolithically etched into the GaN (St Andrews), while the entire structure was to be controlled via a CMOS driver and control IC (Edinburgh). See the image below (Fig#1). 

Fig#1: 2.5D stacking architecture proposed during the HYPIX project, a stack of CMOS driver and control circuitry, a GaN on Sapphire micro-LED structures, nano-imprinted distributed feedback gain cavities and an organic lasing polymer. Image courtesy of E. Fisher.

While the original concept was to use silicon Single-Photon Avalanche Diodes (SPADs) to monitor the optical output, transient behavior and lifetime of the micro-LEDs and organic lasing polymer, the required large-area circuitry for the drivers suggested that the SPAD array should be implemented on a separate IC. This was also performed as the CMOS process for the drivers was sub-optimal for SPADs (high noise), while an ST Microelectronics 130nm imaging process (with 90nm metallization) was shown to have a far superior SPAD performance. 

 

This is where my Ph.D. comes in, as a dedicated SPAD receiver IC of 1024 SPADs in a digital summation and integration mode architecture. The purpose of this IC was two fold, a) to act as a receiver for visible optical communications with either free-space propagation or polymer-optical-fibres and b) to act as a high-sensitivity, high-speed, direct-to-digital photodetector for optical physics research, and the characterisation of both the micro-LEDs and the lasing polymers.

 

Project Outcomes / Conclusions:

 

The HYPIX project suffered from one fundamental issue, being that it was blue sky engineering rather than for any particular application. For example, the above structure was not intended for displays and was not intended directly for communications, it was instead to be an exercise in the feasibility of such structures in order to promote application use at a later date.

Despite this we did obtain:

  • Data reception using an array of SPADs (bare uLED transmission),

  • Lasing of an organic polymer,

  • uLEDs were successfully used to optically pump the lasing material, and

  • CMOS-driven uLEDs were used to transmit data.

 

However, due to finite drive strength, it was not possible to obtain lasing using the CMOS driven bump-bonded uLED structure, and due to time pressures, it was not possible to investigate the use of CMOS-driven uLEDs for communications in an array mode with the SPAD receiver.

 

A Single-Photon Optical Communications Receiver:

 

We developed a 32x32 array of SPADs using an integration mode receiver and digital summation architecture. This leverages the CMOS digital logic level of the SPADs in a sampled discrete time rather than the current steering approach proposed by others to obtain signal summation. The inherent difference being that those architectures incorporate an attenuation, in that a CMOS level signal is used to switch a <100uA current steering, but the combined current must eventually be re-converted into a voltage through a trans-impedance amplifier and must be sampled to obtain the discrete time data stream. 

 

In Fig #2, the SPAD array is shown with labels for its constituent parts. The physical layout of the IC was designed to accept 16 strands of a multi-core polymer optical fibre (POF). These separate regions are shown below as a "Data Channel". In most of the Hypix experiments, however, all SPADs were connected to a global chip 14bit output bus operating with a sample rate of 100MHz. 

 

 

Fig #3 shows a planar view of the CMOS process near the SPAD.

Fig#2: A 32 by 32 array of single-photon avalanche diodes in a 130nm CMOS process. Groups of 4 SPADs are connected to a 6-bit digital pulse counter using a small XOR tree (designed 2010). The IC implements an integrating receiver, taking the sum of all photons arriving within a short, controllable data symbol period. A hierarchy of parallel digital adders takes the summation of these signals to obtain a high signal amplitude from multiple SPADs. Image courtesy of E. Fisher.

Fig#3: The planar structure of the CMOS process, showing the SPAD avalanche multiplication region (P-well to deep N-Well), and the planar structure of the surrounding 'Pixel' circuitry.A passive n-well/p-well guard ring, reverse biased to 1.2V was used around each of the 1024 SPADs in the array, in an attempt to reduce pixel-to-pixel cross talk due to electrons within the bulk CMOS substrate. Image courtesy of E. Fisher.

Chip Highlights:

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Senior Electronics Design Engineer, (Digital)

Coda Octopus Products Ltd.

South Gyle, Edinburgh, Scotland, UK

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Dr Edward M.D. Fisher Ph.D MEng MIEEE MIET