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Core Interests:

  • Imaging Technologies

    • RADAR, SONAR, Tomography, 3D Imaging, LIDAR,

    • CMOS Image Sensors, Electrical Impedance

  • Reconfigurable Digital Systems (ASICs and FPGAs)

    • Verilog HDL, VHDL, RTL, Logic Optimization

    • Clocking and Reset Strategies

    • System Architecture, Control and Real-Time Computation

  • Digital Signal Processing (DSP)

    • Filters, Digital Lock-in Amplifiers (i.e. quadrature)

  • Image Signal Processing (ISP)

  • (*some) Analogue Design

    • Filters, Amplifiers, Signal and Data Acquisition

    • ADCs, DACs, TDCs

    • Power, Digital Systems, Signal Integrity

    • PCB schematic and layout

  • High-speed interfaces such as SerDes and LVDS

  • and Novel Instrumentation and Measurement.



Industry Standards:

  • ISO-9001 (required at Leonardo)

  • DO-254 and ISO 26262 design (required at Leonardo)

  • The Universal Design Methodology (UDM)



Primary Differentiator:

  • Experience of the *entire* electronics chain from:

    • Silicon IC analogue and digital design (ASICs) including layout, floorplanning, modelling, design for test and of course Pad Ring and characterisation.

    • Digital FPGA development using Verilog and other HDLs

      • Optimisation and design re-use

    • Printed circuit board (PCB) schematic and layout including high-speed interfaces (580Mb/s/lane x 16-lane) and signal integrity etc

    • Comfortable with optics, light, radio and acoustic detection, also comfortable at the data protocol levels for Ethernet and other standards.

    • System-level design, interfaces between custom units and COTS modules, system architectures etc

    • System modelling (Matlab, Octave etc) for aiding design choices or explore alternatives.

    • (*some) Project and team management 

    • Full design specification, documentation and, of course, publishable outputs (Journal/Conference).

  • Developing a specialism in digital circuit design...


Career Timeline: Updated April 2019

Industry Experience:

April-2019 to Present:

  • Lumotive LLC (Washington, USA) - SPAD-based LiDAR Receiver Array Project

    • Dates: April 2019 - August 2019

    • Task: SPAD receiver consultancy (ideas, design factors, advice and system-level modelling) as to a high readout rate (2ns bins) multi-channel (256) photon counting receiver array for automotive LiDAR.

    • Working with Dr Gleb Alexrod (Lumotive CTO and Co-Founder) [Link]

  • Leonardo MW (Radar - Edinburgh) - FPGA Firmware / Digital Engineer

    • Digital logic design for Xilinx and Intel FPGAs

    • Languages: Verilog HDL + VHDL, *(soon) SystemVerilog and poss. UVM etc

    • Clearances: UK Baseline Personnel Security Standard (BPSS) and Security Check (SC) - FULLY CLEARED

    • Standards: ISO9001, DO-256, ISO-26262

    • [Leonardo Link]


Sept-2018 to April-2019:

  • Coda Octopus Products Ltd (Sonar - Edinburgh) - SENIOR Electronics / Hardware Engineer

    • Electrical systems design covering:
      - Analogue Filter Design and Test for Military Customers
      - New Product Generation PCB Design (Altium Designer)
      - Algorithm Development and DSP (improved object detection)
      - System-Level and Data Acquisition Architecture and Analysis
      - Feasibility and system level simulation, obsolete part replacement
      - Peer Review for a publication aimed at a SONAR trade-magazine
      - Specifications engineering and robust design documentation
      - Generated proposals for changes to the existing and new designs to aid optimisation and removal of design bottlenecks, e.g. use of managed time-division to reduce cost over a fully-parallel readout scheme.
      - ISO9001 compliance (further reading on DO-256 and ISO-26262)

    • Despite FPGA (Verilog/VHDL), GPU, Microcontroller and Embedded Software being mentioned on the job advert, no tasks utilising these skills were forthcoming simply due to the lack of sufficient work over and above existing FPGA-specific staff. This prompted the move to Leonardo to ensure I kept my existing digital logic specialism progressing.

    • Standards: ISO9001

    • [Coda Octopus Link]


October-2013 to August 2018:

  • The University of Edinburgh (Tomography - Edinburgh) - Post-Doctoral Research Scientist (PDRA)

    • For details see the academic sections of my website [profile], [publications] and [research projects].

    • Industry Project Partners:

      • Rolls-Royce PLC (Derby, Filton and East Kilbride),

      • Instituto Nacional de Técnica Aeroespacial, INTA (Spanish Ministry of Defense and Space Agency)

      • Royal Dutch Shell

      • Optosci

      • Various SMEs and collaborators across academia

    • [School of Engineering Link]


March-2013 to August 2013:

  • Cytomos (Biomedical Electrical Impedance Spectroscopy - Edinburgh) - Development Engineer (Part-Time)

    • Dr Keith Muir at Cytomos developed an ASIC (same PhD research group as myself) able to provide biomedical cell analysis (counting, cell characterisation and sorting) using wide-band electrical impedance spectroscopy to probe the surface membrane and internal structure of biological cell lines.

    • FPGA Firmware Development (Verilog) - development of reconfigurable and parameterised blocks

    • Software Development (Python)

    • ASIC Characterisation (electrode array, microfluidics and readout testing)

    • PCB and development platform debugging

    • Technology and market landscaping to aid Keith's discussions with investors

    • [Cytomos Link]


September-2009 to August 2014:

  • The University of Edinburgh (Single-Photon Avalanche Diodes- Edinburgh) - Doctorate (PhD study)

    • For details see the academic sections of my website [profile], [publications] and [research projects].

    • CMOS single-photon avalanche diodes (SPADs) for low-light optical communications.

    • The chip used a parallel, synchronous summation tree to obtain high-speed direct optical to digital conversion. A variety of quenching methods were used alongside an innovative multi-mode time-division multiplexing method.

    • Sole-development of the IC including schematics, layout, padring, configuration SPI and characterisation.

    • Sole-development of a testing harness PCB and FPGA (Verilog) and PC software (Java) to enable tests for thesis and publication. Optical setups were also required to enable various experiments, processed using Matlab.

    • Modelling and numerical simulation in Matlab, alongside analytical modeling.

    • Experience with common SPAD parameters such as dark count rate (DCR), afterpulsing, gating, readout topologies, quenching circuits, dead time, cross talk, fill factor and the history and literature of these devices.

    • Industry Project Partners:

      • ST Microelectronics (130nm custom-image-sensor CMOS with 90nm metalization)

      • Various collaborators across academia

    • [School of Engineering Link]


May-2008 to December-2008:

  • ST Microelectronics (CMOS Image Sensors - Edinburgh) - 8 Month M.Eng Placement

    • M.Eng project: "Development of Statistically-based Exposure Control Techniques for Mobile Phone Imaging Sensors" - For thesis see: [publications]

    • The project initially centred on a human psychometric study (sex, age and geographic regional factors) for the subjective "perfect" image and camera exposure.

    • Matlab algorithm development looking at image statistics including the Kolmogorov measure, entropy and higher central moments to ascertain the shift in exposure value needed to bring a preliminary 'video-feed' capture into a better exposure region.

    • [ST Microelectronics Link]


June-2007 to August-2007:

  • ST Microelectronics (CMOS Image Sensors - Edinburgh) - 3rd to 4th Year UG Summer Placement

    • I worked on image processing algorithms for a blind raw image file parser. Algorithms and GUI to automatically obtain bit depth, width, length, header size, bit-order and colour mode from RAW Bayer images.

    • This was a great introduction to image processing including colour channel correlation for an automatic preview of the RAW image prior to demosaicing.

    • The GUI was programmed using Python and WX Python widgets, while the back end algorithms were initially designed in Python and ported to C for faster computation with SWIG wrappers for easy python module data flow.

    • [ST Microelectronics Link]

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