The FLITES project (Fibre Laser Imaging of Gas Turbine Exhaust Species), aims to tomographically reconstruct the distribution of pollutant gasses within the hot, high speed exhaust plume of large commercial jet engines. Initially the project has centred upon CO2 and Soot using techniques such as Tunable Diode Laser Absorption Spectroscopy (TDLAS), Wavelength Modulation Spectroscopy (WMS), and Laser-Induced Incandescence (LII).
My role in the project has been quite varied, including elements of budgetting, management, student supervision, and of course electronics hardware, firmware and software development. The overall structure of the project has been particularly challenging as it has required a number of steep leaning curves to be surmounted in order for the system to be operational in the harsh environment of a commercial jet engine testing cell (Rolls Royce).
So what is the system. Well we aim to detect a gas species, say CO2 or Unburnt Hydrocarbons (UHC), with a reasonable spatial resolution as a planar slice normal to the direction of the jet exhaust. By performing this at video frame rates of 100fps, we hope to both spatially and temporally investigate the burning efficiency of the engine, the effects of different fuel mixtures, observe non-ideal engine conditions such as an inactive combustion burner and of course provide Rolls Royce and Shell with a diagnostic testing harness for both existing engine stock and novel engine designs coming into their prototype phase.
The system uses 126 near-infrared laser beams (approx 2um) to detect gas absorption over the lasers path. The beams are positioned into a grid of 6 projections (or angles), with multiple beams per projection to cover an approximate 1.8m diameter primary imaging plane.
From an electrical point of view the harsh testing environment, (high vibration, high air speeds, oils, unburnt fuel and water), prevents long cable runs or analogue signalling. The testing cell is so dangerous infact that no human operator is allowed within the cell during operation. For this reason all signal acquisition is required to be remote, with a cabling distance > 50m.
The PCB design above, is one of twelve custom designed data acquision boards, distributed around the imaging plane. Each samples upto 16 analogue channels at 40MS/s 14bit resolution. The gas sensing technique uses lock-in detection so this has been implemented with a high resolution Direct Digital Synthesis (DDS) module acting as the reference signal. The central FPGA in the PCB design therefore contains 16 SerDes ADC input streams, full automatic bitslip control, upto 16 FPGA-based Digital Lock-In Amplifiers (DLIAs), and data FIFOs and memory for storage.
The FPGA design also contains an embedded microprocesssor system, that manages the acquisition of the data, provides remote control of all registers and packages up the data into Ethernet packets. Being a custom design, Ethernet is no longer simple 'plug and play', however to interface to the testing facility's network the Ethernet protocol must be brought right up to industry standards, including correct headers and cyclic redundancy checks etc.
The complexity of the system has been a major challenge in the project as traditionally COTS solutions such as NI cards circumvent the need to get down to the non-novel industry standard implementations of these communications standards. Even something as simple as grabbing FIFO data from the FPGAs memory and send it using the embedded microprocessor has required the use of Direct Memory Access (DMA), the use of the AXI interconnection standards and the development of custom fabric logic interfaces known as Intellectual Property InterFaces (IPIFs).
Despite the PCB being non-novel from an academic view, the system as a whole will be the first high resolution in space and time measurement harness for jet engine plume diagnostics. And when extended to other wavelengths that are absorbed by other polutant gasses, will provide a window into the chamistry of the jet engine combustion process. All is not lost however in terms of publishing the electronics as we have developed:
a method to mitigate any data loss due to Ethernet packet losses using a method similar to piano error tuning, and
the Ph.D student on the electronics has further developed FPGA-based, Multi-Channel Digital Lock-In technology that is both far smaller and far cheaper than traditional rack mount lab-based DLIs.
Watch this space...